Defines | |||
![]() | ![]() | #define | TIER_ENABLE_ICA |
![]() | ![]() | #define | TIER_ENABLE_ICB |
![]() | ![]() | #define | TIER_ENABLE_ICC |
![]() | ![]() | #define | TIER_ENABLE_ICD |
![]() | ![]() | #define | TIER_ENABLE_OCA |
![]() | ![]() | #define | TIER_ENABLE_OCB |
![]() | ![]() | #define | TIER_ENABLE_OF |
![]() | ![]() | #define | TIER_RESERVED |
![]() | ![]() | #define | TCSR_ICA |
![]() | ![]() | #define | TCSR_ICB |
![]() | ![]() | #define | TCSR_ICC |
![]() | ![]() | #define | TCSR_ICD |
![]() | ![]() | #define | TCSR_OCA |
![]() | ![]() | #define | TCSR_OCB |
![]() | ![]() | #define | TCSR_OF |
![]() | ![]() | #define | TCSR_RESET_ON_A |
![]() | ![]() | #define | TCR_A_RISING |
![]() | ![]() | #define | TCR_B_RISING |
![]() | ![]() | #define | TCR_C_RISING |
![]() | ![]() | #define | TCR_D_RISING |
![]() | ![]() | #define | TCR_BUFFER_A |
![]() | ![]() | #define | TCR_BUFFER_B |
![]() | ![]() | #define | TCR_CLOCK_2 |
![]() | ![]() | #define | TCR_CLOCK_8 |
![]() | ![]() | #define | TCR_CLOCK_32 |
![]() | ![]() | #define | TCR_CLOCK_EXT |
![]() | ![]() | #define | TOCR_OCRA |
![]() | ![]() | #define | TOCR_OCRB |
![]() | ![]() | #define | TOCR_ENABLE_A |
![]() | ![]() | #define | TOCR_ENABLE_B |
![]() | ![]() | #define | TOCR_HIGH_LEVEL_A |
![]() | ![]() | #define | TOCR_HIGH_LEVEL_B |
![]() | ![]() | #define | CR_ENABLE_IRQA |
![]() | ![]() | #define | CR_ENABLE_IRQB |
![]() | ![]() | #define | CR_ENABLE_IRQO |
![]() | ![]() | #define | CR_CLEAR_NEVER |
![]() | ![]() | #define | CR_CLEAR_ON_A |
![]() | ![]() | #define | CR_CLEAR_ON_B |
![]() | ![]() | #define | CR_CLEAR_ON_EXTERN |
![]() | ![]() | #define | CSR_MATCH_A |
![]() | ![]() | #define | CSR_MATCH_B |
![]() | ![]() | #define | CSR_OVERFLOW |
![]() | ![]() | #define | CSR_IGNORE_B |
![]() | ![]() | #define | CSR_0_ON_B |
![]() | ![]() | #define | CSR_1_ON_B |
![]() | ![]() | #define | CSR_TOGGLE_ON_B |
![]() | ![]() | #define | CSR_IGNORE_A |
![]() | ![]() | #define | CSR_0_ON_A |
![]() | ![]() | #define | CSR_1_ON_A |
![]() | ![]() | #define | CSR_TOGGLE_ON_A |
![]() | ![]() | #define | SMR_SYNC |
![]() | ![]() | #define | SMR_ASYNC |
![]() | ![]() | #define | SMR_7BIT |
![]() | ![]() | #define | SMR_8BIT |
![]() | ![]() | #define | SMR_P_NONE |
![]() | ![]() | #define | SMR_P_EVEN |
![]() | ![]() | #define | SMR_P_ODD |
![]() | ![]() | #define | SMR_1STOP |
![]() | ![]() | #define | SMR_2STOP |
![]() | ![]() | #define | SMR_MP |
![]() | ![]() | #define | SMR_CLOCK |
![]() | ![]() | #define | SMR_CLOCK_4 |
![]() | ![]() | #define | SMR_CLOCK_16 |
![]() | ![]() | #define | SMR_CLOCK_64 |
![]() | ![]() | #define | SCR_TX_IRQ |
![]() | ![]() | #define | SCR_RX_IRQ |
![]() | ![]() | #define | SCR_TRANSMIT |
![]() | ![]() | #define | SCR_RECEIVE |
![]() | ![]() | #define | SCR_MP_IRQ |
![]() | ![]() | #define | SCR_TE_IRQ |
![]() | ![]() | #define | SCR_INT_CLOCK |
![]() | ![]() | #define | SCR_EXT_CLOCK |
![]() | ![]() | #define | SCR_CLOCK_OUT |
![]() | ![]() | #define | SSR_TRANS_EMPTY |
![]() | ![]() | #define | SSR_RECV_FULL |
![]() | ![]() | #define | SSR_OVERRUN_ERR |
![]() | ![]() | #define | SSR_FRAMING_ERR |
![]() | ![]() | #define | SSR_PARITY_ERR |
![]() | ![]() | #define | SSR_ERRORS |
![]() | ![]() | #define | SSR_TRANS_END |
![]() | ![]() | #define | SSR_MP |
![]() | ![]() | #define | SSR_MP_TRANSFER |
![]() | ![]() | #define | B2400 |
![]() | ![]() | #define | B4800 |
![]() | ![]() | #define | B9600 |
![]() | ![]() | #define | B19200 |
![]() | ![]() | #define | B38400 |
![]() | ![]() | #define | ADCSR_END |
![]() | ![]() | #define | ADCSR_ENABLE_IRQ |
![]() | ![]() | #define | ADCSR_START |
![]() | ![]() | #define | ADCSR_SCAN |
![]() | ![]() | #define | ADCSR_TIME_266 |
![]() | ![]() | #define | ADCSR_TIME_134 |
![]() | ![]() | #define | ADCSR_GROUP_0 |
![]() | ![]() | #define | ADCSR_GROUP_1 |
![]() | ![]() | #define | ADCSR_AN_0 |
![]() | ![]() | #define | ADCSR_AN_1 |
![]() | ![]() | #define | ADCSR_AN_2 |
![]() | ![]() | #define | ADCSR_AN_3 |
![]() | ![]() | #define | ADCR_EXTERN |
![]() | ![]() | #define | SYSCR_SOFTWARE_STANDBY |
Variables | |||
![]() | ![]() | unsigned char | T_IER |
![]() | ![]() | 16-bit timer interrupt enable register. | |
![]() | ![]() | volatile unsigned char | T_CSR |
![]() | ![]() | 16-bit timer control / status register. | |
![]() | ![]() | volatile unsigned | T_CNT |
![]() | ![]() | 16-bit timer count register. | |
![]() | ![]() | unsigned | T_OCRA |
![]() | ![]() | 16-bit timer output compare register A. | |
![]() | ![]() | unsigned | T_OCRB |
![]() | ![]() | 16-bit timer output compare register B. | |
![]() | ![]() | unsigned char | T_CR |
![]() | ![]() | 16-bit timer control register. | |
![]() | ![]() | unsigned char | T_OCR |
![]() | ![]() | 16-bit timer output control register. | |
![]() | ![]() | volatile unsigned | T_ICRA |
![]() | ![]() | 16-bit timer input capture A register. | |
![]() | ![]() | volatile unsigned | T_ICRB |
![]() | ![]() | 16-bit timer input capture B register. | |
![]() | ![]() | volatile unsigned | T_ICRC |
![]() | ![]() | 16-bit timer input capture C register. | |
![]() | ![]() | volatile unsigned | T_ICRD |
![]() | ![]() | 16-bit timer input capture D register. | |
![]() | ![]() | unsigned char | STCR |
![]() | ![]() | serial / timer control register. | |
![]() | ![]() | unsigned char | T0_CR |
![]() | ![]() | timer 0 control register. | |
![]() | ![]() | volatile unsigned char | T0_CSR |
![]() | ![]() | timer 0 control / status register. | |
![]() | ![]() | unsigned char | T0_CORA |
![]() | ![]() | timer 0 constant A register. | |
![]() | ![]() | unsigned char | T0_CORB |
![]() | ![]() | timer 0 constant B register. | |
![]() | ![]() | volatile unsigned char | T0_CNT |
![]() | ![]() | timer 0 counter register. | |
![]() | ![]() | unsigned char | T1_CR |
![]() | ![]() | timer 1 control register. | |
![]() | ![]() | volatile unsigned char | T1_CSR |
![]() | ![]() | timer 1 control / status register. | |
![]() | ![]() | unsigned char | T1_CORA |
![]() | ![]() | timer 1 constant A register. | |
![]() | ![]() | unsigned char | T1_CORB |
![]() | ![]() | timer 1 constant B register. | |
![]() | ![]() | volatile unsigned char | T1_CNT |
![]() | ![]() | timer 1 counter register. | |
![]() | ![]() | volatile unsigned char | S_RDR |
![]() | ![]() | serial receive data register. | |
![]() | ![]() | unsigned char | S_TDR |
![]() | ![]() | serial transmit data register. | |
![]() | ![]() | unsigned char | S_MR |
![]() | ![]() | serial mode register. | |
![]() | ![]() | unsigned char | S_CR |
![]() | ![]() | serial control register. | |
![]() | ![]() | volatile unsigned char | S_SR |
![]() | ![]() | serial status register. | |
![]() | ![]() | unsigned char | S_BRR |
![]() | ![]() | serial baud rate register. | |
![]() | ![]() | unsigned char | S_TCR |
![]() | ![]() | serial / timer control register. | |
![]() | ![]() | volatile unsigned char | AD_A_H |
![]() | ![]() | A/D converter data register A high. | |
![]() | ![]() | volatile unsigned char | AD_A_L |
![]() | ![]() | A/D converter data register A low. More... | |
![]() | ![]() | volatile unsigned char | AD_B_H |
![]() | ![]() | A/D converter data register B high. | |
![]() | ![]() | volatile unsigned char | AD_B_L |
![]() | ![]() | A/D converter data register B low. More... | |
![]() | ![]() | volatile unsigned char | AD_C_H |
![]() | ![]() | A/D converter data register C high. | |
![]() | ![]() | volatile unsigned char | AD_C_L |
![]() | ![]() | A/D converter data register C low. More... | |
![]() | ![]() | volatile unsigned char | AD_D_H |
![]() | ![]() | A/D converter data register D high. | |
![]() | ![]() | volatile unsigned char | AD_D_L |
![]() | ![]() | A/D converter data register D low. More... | |
![]() | ![]() | volatile unsigned | AD_A |
![]() | ![]() | A/D converter data register A. More... | |
![]() | ![]() | volatile unsigned | AD_B |
![]() | ![]() | A/D converter data register B. More... | |
![]() | ![]() | volatile unsigned | AD_C |
![]() | ![]() | A/D converter data register C. More... | |
![]() | ![]() | volatile unsigned | AD_D |
![]() | ![]() | A/D converter data register D. More... | |
![]() | ![]() | volatile unsigned char | AD_CSR |
![]() | ![]() | A/D converter control / status register. | |
![]() | ![]() | unsigned char | AD_CR |
![]() | ![]() | A/D converter control register. | |
![]() | ![]() | unsigned char | SYSCR |
![]() | ![]() | system control register. | |
![]() | ![]() | unsigned char | PORT1_PCR |
![]() | ![]() | port 1 input pull-up control register. | |
![]() | ![]() | unsigned char | PORT2_PCR |
![]() | ![]() | port 2 input pull-up control register. | |
![]() | ![]() | unsigned char | PORT3_PCR |
![]() | ![]() | port 3 input pull-up control register. | |
![]() | ![]() | unsigned char | PORT1_DDR |
![]() | ![]() | port 1 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT1 |
![]() | ![]() | port 1 I/O register. | |
![]() | ![]() | unsigned char | PORT2_DDR |
![]() | ![]() | port 2 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT2 |
![]() | ![]() | port 2 I/O register. | |
![]() | ![]() | unsigned char | PORT3_DDR |
![]() | ![]() | port 3 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT3 |
![]() | ![]() | port 3 I/O register. | |
![]() | ![]() | unsigned char | PORT4_DDR |
![]() | ![]() | port 4 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT4 |
![]() | ![]() | port 4 I/O register. | |
![]() | ![]() | unsigned char | PORT5_DDR |
![]() | ![]() | port 5 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT5 |
![]() | ![]() | port 5 I/O register. | |
![]() | ![]() | unsigned char | PORT6_DDR |
![]() | ![]() | port 6 data direction register. | |
![]() | ![]() | volatile unsigned char | PORT6 |
![]() | ![]() | port 6 I/O register. | |
![]() | ![]() | volatile unsigned char | PORT7 |
![]() | ![]() | port 7 input register. |
#define TIER_ENABLE_ICA () |
#define TIER_ENABLE_ICB () |
#define TIER_ENABLE_ICC () |
#define TIER_ENABLE_ICD () |
#define TIER_ENABLE_OCA () |
#define TIER_ENABLE_OCB () |
#define TIER_ENABLE_OF () |
#define TIER_RESERVED () |
#define TCSR_ICA () |
#define TCSR_ICB () |
#define TCSR_ICC () |
#define TCSR_ICD () |
#define TCSR_OCA () |
#define TCSR_OCB () |
#define TCSR_OF () |
#define TCSR_RESET_ON_A () |
#define TCR_A_RISING () |
#define TCR_B_RISING () |
#define TCR_C_RISING () |
#define TCR_D_RISING () |
#define TCR_BUFFER_A () |
#define TCR_BUFFER_B () |
#define TCR_CLOCK_2 () |
#define TCR_CLOCK_8 () |
#define TCR_CLOCK_32 () |
#define TCR_CLOCK_EXT () |
#define TOCR_OCRA () |
#define TOCR_OCRB () |
#define TOCR_ENABLE_A () |
#define TOCR_ENABLE_B () |
#define TOCR_HIGH_LEVEL_A () |
#define TOCR_HIGH_LEVEL_B () |
#define CR_ENABLE_IRQA () |
#define CR_ENABLE_IRQB () |
#define CR_ENABLE_IRQO () |
#define CR_CLEAR_NEVER () |
#define CR_CLEAR_ON_A () |
#define CR_CLEAR_ON_B () |
#define CR_CLEAR_ON_EXTERN () |
#define CSR_MATCH_A () |
#define CSR_MATCH_B () |
#define CSR_OVERFLOW () |
#define CSR_IGNORE_B () |
#define CSR_0_ON_B () |
#define CSR_1_ON_B () |
#define CSR_TOGGLE_ON_B () |
#define CSR_IGNORE_A () |
#define CSR_0_ON_A () |
#define CSR_1_ON_A () |
#define CSR_TOGGLE_ON_A () |
#define SMR_SYNC () |
#define SMR_ASYNC () |
#define SMR_7BIT () |
#define SMR_8BIT () |
#define SMR_P_NONE () |
#define SMR_P_EVEN () |
#define SMR_P_ODD () |
#define SMR_1STOP () |
#define SMR_2STOP () |
#define SMR_MP () |
#define SMR_CLOCK () |
#define SMR_CLOCK_4 () |
#define SMR_CLOCK_16 () |
#define SMR_CLOCK_64 () |
#define SCR_TX_IRQ () |
#define SCR_RX_IRQ () |
#define SCR_TRANSMIT () |
#define SCR_RECEIVE () |
#define SCR_MP_IRQ () |
#define SCR_TE_IRQ () |
#define SCR_INT_CLOCK () |
#define SCR_EXT_CLOCK () |
#define SCR_CLOCK_OUT () |
#define SSR_TRANS_EMPTY () |
#define SSR_RECV_FULL () |
#define SSR_OVERRUN_ERR () |
#define SSR_FRAMING_ERR () |
#define SSR_PARITY_ERR () |
#define SSR_ERRORS () |
#define SSR_TRANS_END () |
#define SSR_MP () |
#define SSR_MP_TRANSFER () |
#define B2400 () |
#define B4800 () |
#define B9600 () |
#define B19200 () |
#define B38400 () |
#define ADCSR_END () |
#define ADCSR_ENABLE_IRQ () |
#define ADCSR_START () |
#define ADCSR_SCAN () |
#define ADCSR_TIME_266 () |
#define ADCSR_TIME_134 () |
#define ADCSR_GROUP_0 () |
#define ADCSR_GROUP_1 () |
#define ADCSR_AN_0 () |
#define ADCSR_AN_1 () |
#define ADCSR_AN_2 () |
#define ADCSR_AN_3 () |
#define ADCR_EXTERN () |
#define SYSCR_SOFTWARE_STANDBY () |
unsigned char T_IER |
16-bit timer interrupt enable register.
volatile unsigned char T_CSR |
16-bit timer control / status register.
volatile unsigned T_CNT |
16-bit timer count register.
unsigned T_OCRA |
16-bit timer output compare register A.
unsigned T_OCRB |
16-bit timer output compare register B.
unsigned char T_CR |
16-bit timer control register.
unsigned char T_OCR |
16-bit timer output control register.
volatile unsigned T_ICRA |
16-bit timer input capture A register.
volatile unsigned T_ICRB |
16-bit timer input capture B register.
volatile unsigned T_ICRC |
16-bit timer input capture C register.
volatile unsigned T_ICRD |
16-bit timer input capture D register.
unsigned char STCR |
serial / timer control register.
unsigned char T0_CR |
timer 0 control register.
volatile unsigned char T0_CSR |
timer 0 control / status register.
unsigned char T0_CORA |
timer 0 constant A register.
unsigned char T0_CORB |
timer 0 constant B register.
volatile unsigned char T0_CNT |
timer 0 counter register.
unsigned char T1_CR |
timer 1 control register.
volatile unsigned char T1_CSR |
timer 1 control / status register.
unsigned char T1_CORA |
timer 1 constant A register.
unsigned char T1_CORB |
timer 1 constant B register.
volatile unsigned char T1_CNT |
timer 1 counter register.
volatile unsigned char S_RDR |
serial receive data register.
unsigned char S_TDR |
serial transmit data register.
unsigned char S_MR |
serial mode register.
unsigned char S_CR |
serial control register.
volatile unsigned char S_SR |
serial status register.
unsigned char S_BRR |
serial baud rate register.
unsigned char S_TCR |
serial / timer control register.
volatile unsigned char AD_A_H |
A/D converter data register A high.
volatile unsigned char AD_A_L |
A/D converter data register A low.
bits 0..5 reserved, probably zero
volatile unsigned char AD_B_H |
A/D converter data register B high.
volatile unsigned char AD_B_L |
A/D converter data register B low.
bits 0..5 reserved, probably zero
volatile unsigned char AD_C_H |
A/D converter data register C high.
volatile unsigned char AD_C_L |
A/D converter data register C low.
bits 0..5 reserved, probably zero
volatile unsigned char AD_D_H |
A/D converter data register D high.
volatile unsigned char AD_D_L |
A/D converter data register D low.
bits 0..5 reserved, probably zero
volatile unsigned AD_A |
A/D converter data register A.
bits 0..5 reserved, probably zero
volatile unsigned AD_B |
A/D converter data register B.
bits 0..5 reserved, probably zero
volatile unsigned AD_C |
A/D converter data register C.
bits 0..5 reserved, probably zero
volatile unsigned AD_D |
A/D converter data register D.
bits 0..5 reserved, probably zero
volatile unsigned char AD_CSR |
A/D converter control / status register.
unsigned char AD_CR |
A/D converter control register.
unsigned char SYSCR |
system control register.
unsigned char PORT1_PCR |
port 1 input pull-up control register.
unsigned char PORT2_PCR |
port 2 input pull-up control register.
unsigned char PORT3_PCR |
port 3 input pull-up control register.
unsigned char PORT1_DDR |
port 1 data direction register.
volatile unsigned char PORT1 |
port 1 I/O register.
unsigned char PORT2_DDR |
port 2 data direction register.
volatile unsigned char PORT2 |
port 2 I/O register.
unsigned char PORT3_DDR |
port 3 data direction register.
volatile unsigned char PORT3 |
port 3 I/O register.
unsigned char PORT4_DDR |
port 4 data direction register.
volatile unsigned char PORT4 |
port 4 I/O register.
unsigned char PORT5_DDR |
port 5 data direction register.
volatile unsigned char PORT5 |
port 5 I/O register.
unsigned char PORT6_DDR |
port 6 data direction register.
volatile unsigned char PORT6 |
port 6 I/O register.
volatile unsigned char PORT7 |
port 7 input register.